When a signal synchronized to a first clock signal having a given frequency and phase is received by a receiver running on its own internal clock, i.e., a second clock signal, the received signal is converted into a signal synchronized to the second clock signal so that the received signal can be processed within the receiver. This conversion will hereinafter be referred to as “clock change.” FIG. 1 is a diagram illustrating a first example of the clock change process practiced in the prior art. In the prior art clock change process the received packet data is written to a memory 101 with timing synchronized to the first clock signal CLKt (hereinafter described as the “transmitter clock” in this patent specification) to which the packet data is synchronized. After that, the data is read out of the memory 101 with timing synchronized to the second clock signal CLKr used within the receiver (hereinafter referred to as the “receiver internal clock” in this patent specification), to accomplish the clock change.
For the memory 101 used for the clock change, use can be made of a dual-ported RAM or a FIFO memory. The clock deviation before and after the clock change, i.e., the difference between the transmitter clock CLKt and the receiver internal clock CLKr, can be accommodated by starting to read out the data after a certain amount of data has been accumulated in the memory 101. When the write clock is faster than the read clock, i.e., when the transmitter clock CLKt is faster than the receiver internal clock CLKr, the amount of data accumulated in the memory 101 increases, as depicted in FIG. 2A. Conversely, when the write clock is slower than the read clock, i.e., when the receiver internal clock CLKr is faster than the transmitter clock CLKt, the amount of data accumulated in the memory decreases. A capacity monitoring unit 102 is provided to determine the read start timing of the memory 101 and to check for the presence or absence of data in the memory 101.
FIG. 3 is a diagram illustrating a second example of the clock change process practiced in the prior art. In this method, serial data to which the clock change is to be applied is serial-to-parallel converted by a serial-parallel converter (S/P converter) 111 by sampling the data at sampling times synchronized to the transmitter clock. Since the serial-to-parallel converted data changes with a period equal to (the period of the transmitter clock CLKt)□(the number of bits in the parallel data), the period when the data remains unvarying (hereinafter referred to as the “unvarying period”)becomes longer than that of the original serial data. The unvarying period is thus extended by the serial-to-parallel conversion, and during the unvarying period, the data is converted into serial data synchronized to the receiver internal clock CLKr. In the example illustrated in FIG. 3, the parallel data is stored in a data storing unit 112 during the unvarying period of the parallel data, and the parallel data stored in the data storing unit 112 is converted by a parallel-serial converter 113 into the serial data synchronized to the receiver internal clock.
In the example of FIG. 3, in order to latch the parallel data into the data storing unit 112 at or near the midpoint of the unvarying period, there is provided a timing signal generating unit 114 which generates a latch timing signal that determines the timing for latching the parallel data into the data storing unit 112. The latch timing signal is a signal that rises with a period equal to (the period of the transmitter clock CLKt)□(the bit width of the parallel data) and falls with a period equal to (the period of the receiver internal clock CLKr)□(the bit width of the parallel data). FIG. 4 is a time chart illustrating the clock change process depicted in FIG. 3. The time chart here represents the timing in which the serial data synchronized to the transmitter clock CLKt is converted into 8-bit parallel data by the serial-parallel converter 111. The latch timing signal is generated so that its rising edge is synchronized to a clock whose period is eight times the period T1 of the transmitter clock CLKt and so that its falling edge is synchronized to a clock whose period is eight times the period T2 of the receiver internal clock CLKr.
In the example of FIG. 4, the conversion by the serial-parallel converter 111 is performed in synchronism with the rise timing of the latch timing signal. The falling edge of the latch timing signal is used to latch the data into the data storing unit 112. Further, the rise and fall timings are set so that the latch timing signal has a 50% duty cycle. In this way, the time at which to latch the parallel data into the data storing unit 112 can be set at or near the midpoint of the unvarying period of the parallel data.
If there is a clock deviation between the transmitter clock CLKt and the receiver internal clock CLKr, the duty cycle of the latch timing signal deviates from 50%, and as a result, the time at which to latch the parallel data into the data storing unit 112 becomes displaced from the midpoint of the unvarying period of the parallel data. The timing signal generating unit 114 adjusts the falling edge position of the latch timing signal so as to maintain the duty cycle of the latch timing signal at 50%. However, if the falling edge position of the latch timing signal is adjusted, a data dropout or data duplication may occur when performing the parallel-to-serial conversion. How such errors can occur will be described with reference to FIGS. 5A, 5B, 6A, and 6B.
FIG. 5A is a diagram illustrating the case where the transmitter clock CLKt is faster than the receiver internal clock CLKr. If the transmitter clock CLKt is faster than the receiver internal clock CLKr, the fall timing of the latch timing signal delays, as a result of which the period TH during which the latch timing signal is held at “H” becomes longer than the period TL during which it is held at “L”, as illustrated, and the duty cycle of the latch timing signal thus deviates from 50%.
Suppose that the timing signal generating unit 114 advanced the falling edge position of the latch timing signal by one receiver internal clock CLKr, as depicted in FIG. 5B, in an attempt to maintain the duty cycle of the latch timing signal at 50%. In this case, since the contents stored in the data storing unit 112 are updated before all the bits in the parallel data stored in the data storing unit 112 are converted into the serial data by the parallel-serial converter 113, a data dropout occurs in the resulting serial data.
FIG. 6A is a diagram illustrating the case where the receiver internal clock CLKr is faster than the transmitter clock CLKt. If the receiver internal clock CLKr is faster than the transmitter clock CLKt, the period TH during which the latch timing signal is held at “H” becomes shorter than the period TL during which it is held at “L”, as illustrated, and the duty cycle of the latch timing signal thus deviates from 50%.
Suppose that the timing signal generating unit 114 retarded the falling edge position of the latch timing signal by one receiver internal clock CLKr, as depicted in FIG. 6B. In this case, since the contents stored in the data storing unit 112 are not updated, when all the bits in the parallel data stored in the data storing unit 112 are converted into the serial data by the parallel-serial converter 113, data duplication occurs in the resulting serial data.
Related art is disclosed in Japanese Laid-open Patent Publication No. H02-027834.